Metal films are conventionally utilized in semiconductor manufacturing technology to form electrically conductive contacts to active as well as passive device regions or components formed in or on a semiconductor wafer substrate, as well as for filling via holes, interlevel metallization, and interconnection routing patterns for wiring together the components and/or regions. Because many large scale integration (LSI), very large scale integration (VLSI), and ultra large scale integration (ULSI) devices presently manufactured are very complex and require multiple levels of metallization for interconnections, it has been common to repeat metallization processing multiple times, e.g., to form five or more levels of metallization interconnected by conductive vias. Thus, in the course of manufacturing such devices, each wafer requires passage through one or more metallization systems arranged along a device production line or path.
Metals commonly employed for "back-end" metallization purposes include nickel, titanium, tantalum, aluminum, chromium, gold, silver, copper, and alloys thereof, which metals may be applied to the semiconductor wafers by a variety of techniques, including, but not limited to, electroplating, electroless plating, dipping, pasting, spraying, physical vapor deposition (e.g., evaporation, sputtering, ion plating, plasma spraying, etc.), and chemical vapor deposition (including plasma enhanced chemical vapor deposition). Of the enumerated metals and deposition methods, metallization by electroplated copper or copper-based alloys is particularly attractive for use in LSI, VLSI, and ULSI multilevel metallization systems used for "back-end" processing of semiconductor wafers. Copper and copper-based alloys have very low resistivities, i.e., even lower than that of previously preferred aluminum and aluminum alloys, as well as significantly higher resistance to electromigration. Moreover, copper and its alloys enjoy a considerable cost advantage over a number of the above metals, in particular silver and gold. Lastly, copper and its alloys can be readily deposited in layer form by well-known electroplating techniques, at deposition rates compatible with the requirements of adequate manufacturing throughput.
A significant drawback associated with electroplating systems employed as part of in-line semiconductor manufacturing systems is the inability to measure the plated film properties concurrently with electrodeposition, or at the least, very shortly after withdrawal of the plated semiconductor wafer workpieces from the electroplating bath. Referring to FIG. 1, illustratively shown therein in schematic form, is a diagrammatic top view of a conventional automated or semi-automated "on-track" system 1 which forms a portion of a device manufacturing line, e.g., a manufacturing line for processing semiconductor wafer substrates into a plurality of integrated circuit device regions, which regions are ultimately formed into chips by dicing. On-track automated semiconductor manufacturing systems of the type contemplated for use as herein described may, for example, be obtained from Semitool, Inc. (Kalispell, MT) under the designation LT 210 and suitably adapted for performing electroplating processing as necessary for a particular manufacturing process sequence. The inventive concept is also well adapted for use with alternative arrangements or configurations of process stations and wafer transport mechanisms, such as radially configured apparatus (available from Applied Materials, Santa Clara, Calif.; Novellus, San Jose, Calif.; Semitool, Inc., Kalispell, Mont.; and TEL, Tokyo, Japan) wherein process chambers or stations are arranged in a radial fashion around a central pivoting robot. Moreover, since modern robots and control systems are capable of moving workpieces to or from a number of different locations, the arrangement of process chambers or stations in a radial or linear apparatus need not necessarily be from left to right, but could be from left to right, and then back from right to left, for a number of oscillation cycles.
As illustrated, electroplating system 1 comprises an enclosure 2, a workpiece transport mechanism 3, termed a "track" for transporting workpieces such as semiconductor wafers (not shown) contained in cassette-type workpiece holders 4, 4', each capable of supplying, storing, and receiving a plurality of wafers as they pass through various processing stations along the manufacturing line. In the figure, and simply for the purpose of disclosing the principle of the present invention, workpiece holder 4 on track 3 is shown as transporting into enclosure 2 semiconductor wafer workpieces from an upstream portion of the manufacturing line comprising stations (not shown) for performing antecedent processing, and workpiece holder 4' is illustrated as within the processing enclosure having received plated, post-treated wafer workpieces for storing therein, and as having exited the enclosure via track 3 for supplying the plated, post-treated wafer workpieces to a subsequent processing station (not shown).
Electroplating system 1 comprises from left to right within the enclosure 2 and in the direction of workpiece transport, a first, electroplating station 5 and a second, post-treating station 6 where the just-plated workpieces are rinsed and dried prior to exiting the enclosure. It is to be understood that both cassette-type workpiece holders 4, 4' as shown in the drawing for illustrative purposes only, are identically capable of supplying, storing, and receiving wafer workpieces, as necessary, for performing sequential processing thereof as described.
Located exteriorly of the enclosure 2 (i.e., "stand-alone" placement) is a third, measuring station 7 for determining at least one film characteristic of a representative sample 8 of the just-plated workpieces, e.g., electrical resistivity, thickness, and reflectivity, for determining whether proper electroplating and rinsing/drying conditions have been established in first and second stations 5, 6, respectively, and for adequate quality assurance. Specifically, measurement of film resistivity, as by use of a 4-point probe or a contactless device comprising third station 7, is essential for determining whether electrical connections of sufficiently low resistivity have been established as a result of the electroplating; adequate film thickness is necessary for ensuring complete surface coverage as well as sufficient electrical conductivity. Reflectivity is indicative of the overall quality and effectiveness of the electroplating, e.g., bright copper plating.
A number of drawbacks are associated with such conventional manufacturing technology as a consequence of the "stand alone" placement of the third, measuring station 7. For example, if the workpiece transfer mechanism, i.e., track 3, is shut down for removal of the test wafer 8, periodic withdrawal and testing of a plated wafer workpiece 8 necessarily entails lost productivity. Should the production line continue to run during testing (for making the same or a different product), and the testing indicates one or more substantial deviations from standard, desired film characteristics, there is a significant risk of producing "out-of-spec" product. A further drawback of the "stand alone" testing arrangement is the inability to rapidly adjust plating conditions in response to film measurement. Nor is it possible to conveniently re-cycle out-of-spec wafers for an additional pass through the electroplating system 1 to increase under-spec film thicknesses and/or decrease over-spec resistivities to acceptable levels.
Thus, there exists a need for an "on-track" process and system which overcomes the above-described drawbacks associated with conventional high-throughput, automated, track type manufacturing apparatus, particularly as employed in the metallization of LSI, VLSI, and ULSI semiconductor devices having multiple metallization levels. Moreover, there exists a need for an improved "on-track" process and apparatus for electroplating and post-treatment of semiconductor wafers for metallization thereof, which process and apparatus are fully compatible with the balance of conventional semiconductor manufacturing lines.